x86 and Arm Rival, RISC-V Architecture ships 10 billion cores

x86 & Arm Rival, RISC-V Architecture Ships 10 Billion Cores
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Calista Redmond, CEO of RISC-V International, announced at Embedded World that there are currently ten billion RISC-V cores on the market.

ARM RISC-V architecture has shipped 10 billion cores and is reportedly more prominent than x86 and Arm architecture for the future

RISC-V, pronounced “risk five”, is an open standard instruction set architecture (ISA) provided under open source licenses that are free to use. The basic instruction set has 32-bit fixed-length naturally aligned instructions, and the ISA supports variable-length extensions, which means that each instruction can be of any numerical length within 16-bit packets. The instruction set comes in 32-bit and 64-bit address space flavors and is built for a wide range of uses. Various subassemblies support everything from tiny embedded systems to PCs, supercomputers with vector processors, and warehouse-scale rack-mounted parallel computers.

Calista Redmond said that open standards are the key.

Linux is doing this for software and we are doing this for hardware. We estimate that there are 10 billion RISC-V cores on the market.

But, the road to ten billion was not a quick task. It is reported that it took seventeen years of trial and error for the ARM architecture to achieve the milestone in 2008. On the other hand, RISC-V only took twelve years to complete ten billion. Redmond anticipates that the number of RISC-V processor cores is projected to reach eighty billion by 2025.

Source: Embedded World 2022.

Included with this news was the announcement of the consent of the four new specifications and extensions from this year. the four new specifications are:

  • The RISC-V specification for SBI designs a firmware layer between the hardware platform and the operating system kernel using a supervisor-mode (S-mode or VS-mode) application binary interface. This abstraction enables common platform services across all implementations of the RISC-V operating system. Many RISC-V members have already implemented the RISC-V SBI specification in their RISC-V solutions, so ratification of the specification will ensure a standard approach throughout the RISC-V ecosystem, ensuring compatibility. The development and ratification of this specification was carried out by Atish Patra de Rivos, with the work carried out by the Horizontal Steering Committee of the Platform.
  • The RISC-V UEFI protocols bring the existing UEFI standards to the RISC-V platforms. This specification was developed and ratified by Sunil VL, Ventana Micro, and Philipp Tomsich, VRULL GmbH, with work done in the Privileged Software Technical Working Group.
  • E-Trace for RISC-V defines a highly efficient approach to processor tracing using branch tracing, ideal for debugging any type of application, from small embedded designs to super powerful computers. The E-Trace documentation for RISC-V specifies the signals between the RISC-V core and the encoder (or input port), a compressed branch trace algorithm, and a packet format for encapsulating the compressed branch trace information. . This specification was developed and ratified by Gajinder Panesar of Picocom and the RISC-V E-Trace Working Group.
  • RISC-V Zmmul Multiply Only enables low-cost implementations that require multiplication but not division operations and is part of the RISC-V non-privileged specification. The development and ratification of this extension was led by Allen Baum, with work done on the ISA Committee without privileges.

news sources: IT startup,

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